Terence B. Hook
207Patents
18h-index
186Co-inventors
89Inventor score
Filing activity: Nov 22, 1994 → Jun 15, 2022
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7132323B2 | CMOS well structure and method of forming the same | Electricity | 98 | Expired |
| US5972765A | Use of deuterated materials in semiconductor processing | Electricity | 93 | Expired |
| US7067886B2 | Method of assessing potential for charging damage in SOI designs and structures for eliminating potential for damage | Electricity | 92 | Expired |
| US6239649A | Switched body SOI (silicon on insulator) circuits and fabrication method therefor | Electricity | 54 | Expired |
| US5898196A | Dual EPI active pixel cell design and method of making the same | Electricity | 42 | Expired |
| US6083794A | Method to perform selective drain engineering with a non-critical mask | Electricity | 33 | Expired |
| US6026964A | Active pixel sensor cell and method of using | Electricity | 31 | Expired |
| US9490335B1 | Extra gate device for nanosheet | Emerging Cross-Sectional Technologies | 27 | Active |
| US9805935B2 | Bottom source/drain silicidation for vertical field-effect transistor (FET) | Electricity | 27 | Active |
| US8619979B2 | Physically unclonable function implemented through threshold voltage comparison | Electricity | 27 | Active |
| US6194702A | Method of forming a complementary active pixel sensor cell | Electricity | 25 | Expired |
| US9515138B1 | Structure and method to minimize junction capacitance in nano sheets | Electricity | 24 | Active |
| US6956417B2 | Leakage compensation circuit | Electricity | 23 | Expired |
| US9431388B1 | Series-connected nanowire structures | Electricity | 23 | Active |
| US6489223B1 | Angled implant process | Electricity | 22 | Expired |
| US6307805A | High performance semiconductor memory device with low power consumption | Electricity | 22 | Expired |
| US10607938B1 | Power distribution networks for monolithic three-dimensional semiconductor integrated circuit devices | Electricity | 21 | Active |
| US9711501B1 | Interlayer via | Electricity | 21 | Active |
| US5562770A | Semiconductor manufacturing process for low dislocation defects | Emerging Cross-Sectional Technologies | 18 | Expired |
| US9583486B1 | Stable work function for narrow-pitch devices | Electricity | 16 | Active |
| US6022770A | NVRAM utilizing high voltage TFT device and method for making the same | Electricity | 16 | Expired |
| US9761712B1 | Vertical transistors with merged active area regions | Electricity | 14 | Active |
| US9009638B1 | Estimating transistor characteristics and tolerances for compact modeling | Physics | 13 | Active |
| US8552500B2 | Structure for CMOS ETSOI with multiple threshold voltages and active well bias capability | Electricity | 13 | Active |
| US6256755A | Apparatus and method for detecting defective NVRAM cells | Physics | 13 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.