Method and apparatus for verifying timing rules for an integrated circuit design
US6023567A · kind A · utility
12Cited by
20References
26Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 7, 1996 |
| Grant date | Feb 8, 2000 |
| Priority date | — |
| Expiry date | Oct 7, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/3312
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An automated process for timing rule verification for an integrated circuit design is disclosed. The process includes the step of checking the generated timing rules by comparing a given timing rule against a synthesized model to determine timing relationships in the model that are not included in the timing rule and timing relationships in the timing rule that are not present in the model.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.