Method for verifying hold time in integrated circuit design
US6023767A · kind A · utility
4Cited by
4References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 5, 1997 |
| Grant date | Feb 8, 2000 |
| Priority date | — |
| Expiry date | May 5, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for verifying proper communication between a first circuit and a second circuit of an electronic device. First it is determined which global clocks the first circuit and the second circuit are timed by. Then, the clock signal is shifted between the first and second storage circuits by an amount equal to or greater than a global clock skew budget of the device if it is determined that the first and second storage circuits are timed by different global clocks. Finally, verifying proper operation of the second circuit against a local clock skew budget of the device is done.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.