Self aligned DMOS transistor and method of fabrication

US6025231A · kind A · utility

Assignee

• TEXAS INSTRUMENTS INCORPORATED · US

Inventors

• Louis N. Hutter · Richardson, US
• John P. Erdeljac · Plano, US
• James Robert Todd · Plano, US

Key dates

• Filing date: Feb 18, 1998
• Grant date: Feb 15, 2000
• Expiry date: Feb 18, 2018

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/516

Abstract

A method for fabricating a self-aligned DMOS transistor is provided. The method includes forming a passivation layer (18, 68) on an oxide layer (16, 66) of a substrate (12, 56). The oxide layer (16, 66) is then removed from the surface of the substrate (12, 56) where it is exposed through the passivation layer (18, 68). A reduced surface field region (36, 74) is then formed where the surface of the substrate (12, 56) is exposed through the passivation layer (18, 68). An oxide layer (38, 80) is then formed on the reduced surface field region (36, 74).