Underlayer process for high O.sub.3 /TEOS interlayer dielectric deposition
US6025263A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 11, 1997 |
| Grant date | Feb 15, 2000 |
| Priority date | — |
| Expiry date | Sep 11, 2017 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/958
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A underlayer process for high O.sub.3 /TEOS interlayer dielectric deposition is disclosed. First, a layer of metal pattern is defined on a semiconductor substrate, then a layer of dielectric underlayer is deposited, next, a high O.sub.3 /TEOS interlayer dielectric is formed to achieve planarization. The key point of this process is to apply materials with higher refraction index than conventional PE-TEOS for forming interlayer dielectric underlayer. The mentioned material can be PE-SiH.sub.4 with a constant or decreasing refraction index with the distance from the semiconductor substrate. The underlayer can also be bi-layer structure consisting of high refraction index bottom layer and low refraction index surface layer. This invention can effectively suppress the problem caused from high surface sensitivity of O.sub.3 /TEOS, and improve the quality of interlayer dielectric planarization process dramatically.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.