Nonvolatile memory cell
US6025626A · kind A · utility
11Cited by
1References
4Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Mar 23, 1999 |
| Grant date | Feb 15, 2000 |
| Priority date | — |
| Expiry date | Mar 23, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
Abstract
The invention relates to a self-adjusted nonvolatile memory cell, in which a MOS transistor with source and drain regions is incorporated into the surface region of a semiconductor body. The floating gate and the control gate of the MOS transistor are accommodated, overlapping one another, in a recess trench, while the transistor channel is guided laterally in a surface region of the trench.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.