Parallel test circuit for semiconductor memory
US6026039A · kind A · utility
31Cited by
1References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 17, 1998 |
| Grant date | Feb 15, 2000 |
| Priority date | — |
| Expiry date | Dec 17, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5006
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A parallel test circuit for a semiconductor memory device includes multiple data input pads, multiple data input buffers respectively connected to the data input pads for receiving write data in response to a chip selection signal during normal operation, and a switching circuit for electrically connecting the data input pads to each other in response to a current leakage test signal applied to the circuit. The circuit enables the detection of leakage current in the input data buffers at the same time that a parallel data writing test is performed, thereby reducing the total time required to test the device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.