FPGA logic cell internal structure including pair of look-up tables
US6026227A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 24, 1997 |
| Grant date | Feb 15, 2000 |
| Priority date | — |
| Expiry date | Sep 24, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17728
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A field programmable gate array has a matrix of programmable logic cells and a bus network of local and express bus lines. The bus network effectively partitions the matrix into blocks of cells with each block having its own distinct set of local bus lines. Express bus lines extend across more than one block of cells by means of repeater switch units that also connect local bus lines to express bus lines. The grouping of cells into blocks with repeaters aligned in rows and columns at the borders between blocks creates spaces at the corners of blocks that can be filled with RAM blocks, other memory structures, specialized logic structures or other dedicated function elements that are connected to the bus network. The RAM blocks can be single or dual port SRAM addressed through the bus lines. Pairs of adjacent columns of RAM blocks may be commonly addressed by the same set of bus lines. Other specialized or dedicated logic might also fill those corner spaces. Logic cells are directly connected to neighboring cells, including diagonally adjacent cells, and are also connected to local bus lines. The arrangement of express bus lines is preferably staggered in such a way that they connec…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.