Memory simulation system and method
US6026230A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 5, 1998 |
| Grant date | Feb 15, 2000 |
| Priority date | — |
| Expiry date | Feb 5, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/331
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The SEmulation system provides four modes of operation: (1) Software Simulation, (2) Simulation via Hardware Acceleration, (3) In-Circuit Emulation (ICE), and (4) Post-Simulation Analysis. At a high level, the present invention may be embodied in each of the above four modes or various combinations of these modes. At the core of these modes is a software kernel which controls the overall operation of this system. The main control loop of the kernel executes the following steps: initialize system, evaluate active test-bench processes/components, evaluate clock components, detect clock edge, update registers and memories, propagate combinational components, advance simulation time, and continue the loop as long as active test-bench processes are present. The Memory Mapping aspect of the invention provides a structure and scheme where the numerous memory blocks associated with the user's design is mapped into the SRAM memory devices in the Simulation system instead of inside the logic devices, which are used to configure and model the user's design. The Memory Mapping or Memory Simulation system includes a memory state machine, an evaluation state machine, and their associated logic t…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.