Ping-Sheng Tseng
19Patents
14h-index
20Co-inventors
78Inventor score
Filing activity: Sep 29, 1995 → Dec 31, 2020
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6810442B1 | Memory mapping system and method | Physics | 217 | Expired |
| US6389379B1 | Converification system and method | Physics | 184 | Expired |
| US6321366A | Timing-insensitive glitch-free logic system and method | Physics | 154 | Expired |
| US6009256A | Simulation/emulation system and method | Physics | 147 | Expired |
| US6134516A | Simulation server system and method | Physics | 125 | Expired |
| US6026230A | Memory simulation system and method | Physics | 107 | Expired |
| US6785873B1 | Emulation system with multiple asynchronous clocks | Physics | 92 | Expired |
| US6651225B1 | Dynamic evaluation logic system and method | Physics | 89 | Expired |
| US7512728B2 | Inter-chip communication system | Physics | 49 | Expired |
| US5809283A | Simulator for simulating systems including mixed triggers | Physics | 48 | Expired |
| US5784593A | Simulator including process levelization | Physics | 25 | Expired |
| US7480606B2 | VCD-on-demand system and method | Physics | 23 | Expired |
| US8244512B1 | Method and apparatus for simulating a circuit using timing insensitive glitch-free (TIGF) logic | Physics | 21 | Active |
| US9195784B2 | Common shared memory in a verification system | Physics | 17 | Active |
| US9026966B1 | Co-simulation methodology to address performance and runtime challenges of gate level simulations with, SDF timing using emulators | Physics | 9 | Active |
| US8161439B2 | Method and apparatus for processing assertions in assertion-based verification of a logic design | Physics | 4 | Active |
| US8161502B2 | Method and apparatus for implementing a task-based interface in a logic verification system | Physics | 2 | Active |
| US11308008B1 | Systems and methods for handling DPI messages outgoing from an emulator system | Physics | 1 | Active |
| US7991605B1 | Method and apparatus for translating a verification process having recursion for implementation in a logic emulator | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.