VLSIC patterning process
US6027861A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 20, 1998 |
| Grant date | Feb 22, 2000 |
| Priority date | — |
| Expiry date | Mar 20, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/31116
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for etching of sub-quarter micron openings in insulative layers for contacts and vias is described. The method uses high resolution DUV photolithography. By using a thin layer of photoresist to pattern a hardmask, full advantage of the high resolution can be attained. The hardmask in turn, is sufficiently durable to withstand subsequent etching of the insulative layer. The methods taught by this invention are of particular value for the formation of contacts to semiconductive devices although they are also applied to forming via openings. DUV photoresists having thicknesses of less than 500 nm are used with a DUV stepper. The hardmask materials include Ti/TiN and amorphous silicon. Etching selectivities of these materials with respect to typical insulative materials used in integrated circuit manufacture are of the order of 50:1.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.