CMOS semiconductor devices and method of formation

US6027961A · kind A · utility

Assignee

• Motorola, Inc. · US

Inventors

• Bikas Maiti · Austin, US
• Philip J. Tobin · Austin, US
• C. Joseph Mogab · Austin, US
• Christopher C. Hobbs · Austin, US
• Larry E. Frisa · Round Rock, US

Key dates

• Filing date: Jun 30, 1998
• Grant date: Feb 22, 2000
• Expiry date: Jun 30, 2018

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/856

Abstract

In one embodiment, a metal layer (18) is formed over a gate dielectric layer (14, 16) on a semiconductor substrate. A masking layer (20) is patterned to mask a portion of the metal layer (18). An exposed portion of the metal layer (18) is nitrided to form a conductive nitride layer (24). The masking layer (20) is removed and the conductive nitride layer (24) is patterned to form a first gate electrode (23) having a first work function value, and the conductive layer (18) is patterned to form a second gate electrode (25) having a second work function value which is different from that of the first work function value.