Method of making a fin-like stacked capacitor

US6027967A · kind A · utility

Assignee

• Micron Technology, Inc. · US

Inventors

• Kunal R. Parekh · Boise, US
• Zhiqiang Wu · Plano, US
• Li Li · Endicott, US

Key dates

• Filing date: Jul 3, 1997
• Grant date: Feb 22, 2000
• Expiry date: Jul 3, 2017

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D1/711

Abstract

A method of making a capacitor comprising providing a space extending between a pair of gate stacks on a semiconductor substrate, the space exposing a charge conducting region on the semiconductor substrate. A BPSG layer is formed over the pair of gate stacks. A hard mask layer comprising alternating layers of doped polysilicon and undoped polysilicon is formed over the BPSG layer during a single deposition cycle of depositing polysilicon. Portions of the hard mask layer and the BPSG layer are selectively removed to form topographical structures extending above the gate stacks and having a trench therebetween. A spacer etch and a contact etch are performed to expose the charge conducting region. A doped polysilicon spacer is formed on the lateral side of each topographical structure. A second group of alternating layers of doped polysilicon and undoped polysilicon is formed over the topographical structures and within the trench. Portions of the hard mask layer and the second group of the alternating layers of doped polysilicon and undoped polysilicon are selectively removed. An etch selective to the doped polysilicon is performed to selectively remove the undoped polysilicon to cr…