IC stack utilizing secondary leadframes
US6028352A · kind A · utility
122Cited by
14References
9Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 10, 1998 |
| Grant date | Feb 22, 2000 |
| Priority date | — |
| Expiry date | Jun 10, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A structure and process are disclosed in which IC chip-containing layers are stacked to create electronic density. Each layer is formed by mechanically and electrically joining an IC-containing TSOP with an external leadframe. Each leadframe contains conductors which are disposed to connect with TSOP leads, transpose signals to other locations on the periphery of the TSOP, and/or connect with other layers in the stack. The TSOP/leadframe layers are stacked and joined, and the leadframe terminals of the lowest layer are disposed to facilitate connection with a PCB or other circuitry.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.