Programmable clock manager for a programmable logic device that can generate at least two different output clocks
US6028463A · kind A · utility
16Cited by
14References
24Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 15, 1997 |
| Grant date | Feb 22, 2000 |
| Priority date | — |
| Expiry date | Oct 15, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0891
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A programmable logic device (PLD), such as a field programmable gate array (FPGA), has a programmable clock manager (PCM) that converts an input clock into at least two different output clocks having different clock rates. The different output clocks can be used to control different processes either within or outside the FPGA. For example, one output clock can be used to control the FPGA's input/output registers, while a second, faster output clock can be used to control the FPGA's internal registers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.