Stacked bottom lead package in semiconductor devices and fabricating method thereof
US6030858A · kind A · utility
21Cited by
4References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 19, 1997 |
| Grant date | Feb 29, 2000 |
| Priority date | — |
| Expiry date | Nov 19, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention relates to a stacked bottom lead package in semiconductor devices and a method thereof. More specifically, comprising leads that are bent along with the circumference of the body which has been premolded, wherein a chip is include inside the premolded body. The package and the method thereof according to the present invention enable a dual process, decreasing solder fatigue of the lead by carrying heat via the extended leads and emitting the heat out of the chip, and decreasing the area required for stacking semiconductor packages.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.