Vertical NPN transistor for 0.35 micrometer node CMOS logic technology
US6030864A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 11, 1997 |
| Grant date | Feb 29, 2000 |
| Priority date | — |
| Expiry date | Apr 11, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0109
Abstract
A method of fabricating a bipolar transistor concurrently with an MOS device comprising the steps of forming an NPN bipolar transistor by providing a semiconductor wafer (1) having a semiconductor region (3) of predetermined conductivity type having a surface. An emitter region (33) and a collector contact region (35) are formed in and extend to the surface of the semiconductor region (3) of predetermined conductivity type with an implant of the predetermined conductivity type. An intrinsic base region (43) is formed extending to the surface by implanting an impurity of opposite conductivity type in the semiconductor region (3) isolating the emitter region (33) from the semiconductor region of predetermined conductivity type. An insulating layer (49) is formed on the semiconductor region of predetermined conductivity type extending over all transitions at the surface of the predetermined conductivity type to the opposite conductivity type. A portion of the intrinsic base region (43) is then converted to an extrinsic base region (43). A portion of the collector contact (35), a portion of the emitter region (33) and a portion of the extrinsic base region (43) extend to the surface an…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.