Frank Scott Johnson
44Patents
11h-index
34Co-inventors
75Inventor score
Filing activity: Jan 3, 1977 → Oct 24, 2019
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US8603893B1 | Methods for fabricating FinFET integrated circuits on bulk semiconductor substrates | Electricity | 39 | Active |
| US7687339B1 | Methods for fabricating FinFET structures having different channel lengths | Electricity | 28 | Active |
| US8039326B2 | Methods for fabricating bulk FinFET devices having deep trench isolation | Electricity | 24 | Active |
| US4201428A | Cabinet assembly | Human Necessities | 22 | Expired |
| US7960287B2 | Methods for fabricating FinFET structures having different channel lengths | Electricity | 22 | Active |
| US4090755A | Cabinet assembly | Human Necessities | 21 | Expired |
| US8383503B2 | Methods for forming semiconductor structures using selectively-formed sidewall spacers | Electricity | 19 | Active |
| US6030864A | Vertical NPN transistor for 0.35 micrometer node CMOS logic technology | Electricity | 17 | Expired |
| US8404592B2 | Methods for fabricating FinFET semiconductor devices using L-shaped spacers | Electricity | 13 | Active |
| US8912603B2 | Semiconductor device with stressed fin sections | Electricity | 13 | Active |
| US6130136A | Bipolar transistor with L-shaped base-emitter spacer | Electricity | 11 | Expired |
| US8268727B2 | Methods for fabricating FinFET semiconductor devices using planarized spacers | Electricity | 11 | Active |
| US7829466B2 | Methods for fabricating FinFET structures having different channel lengths | Electricity | 9 | Active |
| US7977174B2 | FinFET structures with stress-inducing source/drain-forming spacers and methods for fabricating the same | Electricity | 9 | Active |
| US6570242B1 | Bipolar transistor with high breakdown voltage collector | Electricity | 8 | Expired |
| US9000534B2 | Method for forming and integrating metal gate transistors having self-aligned contacts and related structure | Electricity | 7 | Active |
| US8039349B2 | Methods for fabricating non-planar semiconductor devices having stress memory | Electricity | 7 | Active |
| US8729609B2 | Integrated circuits including multi-gate transistors locally interconnected by continuous fin structure and methods for the fabrication thereof | Electricity | 6 | Active |
| US8030144B2 | Semiconductor device with stressed fin sections, and related fabrication methods | Electricity | 6 | Active |
| US7985639B2 | Method for fabricating a semiconductor device having a semiconductive resistor structure | Electricity | 6 | Active |
| US4208098A | Odor dispensing system for hand-held stereoscopic viewer and replaceable container therefor | Physics | 6 | Expired |
| US9257325B2 | Semiconductor structures and methods for forming isolation between Fin structures of FinFET devices | Electricity | 6 | Active |
| US6518111B1 | Method for manufacturing and structure of semiconductor device with dielectric diffusion source and CMOS integration | Electricity | 5 | Expired |
| US7910422B2 | Reducing gate CD bias in CMOS processing | Electricity | 5 | Active |
| US7930656B2 | System and method for making photomasks | Physics | 4 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.