Method of fabricating mixed-mode device
US6030872A · kind A · utility
4Cited by
2References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 1, 1999 |
| Grant date | Feb 29, 2000 |
| Priority date | — |
| Expiry date | Feb 1, 2019 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/981
Abstract
A method for fabricating a mixed-mode device. A first gate oxide layer and a second gate oxide layer are formed. The polysilicon layer is used as a mask to pattern the gate oxide layers. Additionally, a top electrode is formed during the first gate oxide layer is patterned. A bottom electrode is formed during the second gate oxide layer is patterned. The first gate oxide layer and the second gate oxide layer are formed by a single oxidation operation, thus thicknesses of the first gate oxide layer and the second oxide layer can be effectively controlled.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.