Enhancing DMOS device ruggedness by reducing transistor parasitic resistance and by inducing breakdown near gate runners and termination area
US6031265A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 16, 1997 |
| Grant date | Feb 29, 2000 |
| Priority date | — |
| Expiry date | Oct 16, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/519
Abstract
This invention discloses a vertical DMOS power device formed in a semiconductor substrate with a top surface and a bottom surface. The power device includes a core cell area and a gate runner area. The power device includes a plurality of vertical DMOS transistor cells disposed in the core cell area wherein each transistor cell includes a drain of a first conductivity type disposed at the bottom surface of the substrate. Each of the DMOS transistor cells further includes a trench surrounding the cell having a polysilicon disposed in the trench defining a gate for the transistor cell. Each of the transistor cells further includes a source region of the first conductivity type disposed in the substrate near the gate. Each of the transistor cells further includes a body region of a second conductivity type disposed in the substrate between the gate wherein the body region defining a vertical current channel along the trench between the source and the drain. The power device further includes a plurality of trenched polysilicon fingers extended from the trenched gate to the gate runner area. The power device further includes a plurality of ruggedness enhancing body dopant regions of the…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.