Semiconductor test system with integrated test head manipulator and device handler
US6031387A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 2, 1997 |
| Grant date | Feb 29, 2000 |
| Priority date | — |
| Expiry date | Dec 2, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/2893
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A semiconductor integrated circuit test system, for testing semiconductor integrated circuit devices includes a test head containing pin electronics circuits and a device handler for receiving semiconductor integrated circuit devices to be tested and delivering the devices to a test station for engagement with the test head. The device handler includes a mechanical support structure, a test head manipulator having a first part rigidly attached to the mechanical support structure, a second part which is movable relative to the first part and to which the test head is attached, and a motor effective between the first and second parts of the manipulator for moving the second part relative to the first part. A power server is attached to the device handler independently of the test head manipulator. A cable connects the power server to the pin electronics circuits of the test head.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.