Integrated circuit I/O interface that uses excess data I/O pin bandwidth to input control signals or output status information
US6031767A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 18, 1996 |
| Grant date | Feb 29, 2000 |
| Priority date | — |
| Expiry date | Sep 18, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/126
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An I/O interface for an integrated circuit (IC) is described that has a reduced number of I/O pins dedicated to providing control signals to or status information from the IC. In one embodiment, the IC comprises a plurality of input pins connected to logic for receiving and processing input data. The input pins have an input bandwidth greater than the logic's processing rate. If data and control signals are multiplexed onto the same input pin, the excess input pin bandwidth may used to transfer control signals into a plurality of latches within the IC. The I/O interface outputs a select signal that designates when an external device should drive the input pins with either data or control signals. In a specific embodiment, the logic comprises a parallel to serial converter and the control signal select conversion speed or encoding options. In another embodiment, the IC comprises a plurality of output pins connected to the output of a selector. Status latches and logic for outputting processed data drive the selector's inputs. The IC outputs a select signal that allows an external device to determine when the output pins are carrying processed data versus status information and thus …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.