Semiconductor integrated circuit
US6031788A · kind A · utility
19Cited by
2References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 8, 1998 |
| Grant date | Feb 29, 2000 |
| Priority date | — |
| Expiry date | Dec 8, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1072
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor integrated circuit is adapted to make invalid an external clock, externally supplied to the semiconductor integrated circuit, when the semiconductor integrated circuit is set in an active power-down state. The semiconductor integrated circuit includes a delay locked loop DLL circuit which outputs an internal clock which phase is synchronized to the external clock. A latch circuit retains control signals in synchronism with the internal clock output by the DLL circuit. An internal circuit performs a predetermined process based on the control signals supplied from the latch circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.