Fast RAM for use in an address translation circuit and method of operation
US6032241A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 17, 1997 |
| Grant date | Feb 29, 2000 |
| Priority date | — |
| Expiry date | Dec 17, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/1054
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
There is disclosed, for use in an x86-compatible processor having a physically-addressable cache, an address translation device for translating linear addresses received from a plurality of linear address sources and selectively accessing physical addresses, linear addresses, and controls signals stored in the address translation device. The address translation device comprises: 1) an array of data cells for storing the physical addresses, linear addresses, and controls signals in a plurality of entries; 2) an entry selection circuit for receiving a first linear address from a first linear address source and, in response thereto, generating an entry select output corresponding to the first linear address; 3) a first switch controllable by the entry select output; and 4) a second switch controllable by an address source select signal received from the first linear address source, wherein the entry select output and the address source select signal close the first and second switches to thereby form a connection path, the formation of the connection path causing a selected data cell to transfer a stored target bit stored therein to a data bit line of the address translation device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.