Method and structure to reduce latch-up using edge implants

US6033949A · kind A · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Faye D. Baker · Burlington, US
• Jeffrey S. Brown · Jeffersonville, US
• Robert J. Gauthier, Jr. · South Burlington, US
• Steven J. Holmes · Colchester, US
• Robert K. Leidy · Burlington, US
• Edward J. Nowak · South Burlington, US
• Steven H. Voldman · South Burlington, US

Key dates

• Filing date: Jun 30, 1998
• Grant date: Mar 7, 2000
• Expiry date: Jun 30, 2018

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10S148/137

Abstract

The preferred embodiment of the present invention overcomes the limitations of the prior art and provides a device and method to increase the latch-up immunity of CMOS devices by forming implants at the well edges. The preferred method uses hybrid resist to form these implants at the edges of the N-wells and/or P-wells. The implants reduce the lifetime of minority carriers in the parasitic transistor, and hence reduce the gain of the parasitic transistor. This reduces the propensity of the CMOS device to latch-up. The preferred embodiment method allows these implants to be formed without requiring additional masking steps over prior art methods. Furthermore, the preferred method for forming the implants results in implants that are self aligned to the edges of the wells.