Process for fabricating mixed signal integrated circuit
US6033965A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 28, 1999 |
| Grant date | Mar 7, 2000 |
| Priority date | — |
| Expiry date | Jul 28, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/811
Abstract
A process for fabricating a mixed signal integrated circuit on a substrate, wherein the substrate is partially covered with a field oxide layer. An oxide layer is formed over a portion of the substrate, wherein the portion of the substrate is not covered with the field oxide layer. First impurities are implanted into the substrate, wherein the first impurities damage the oxide layer. A buffer layer is formed over the oxide layer. A polysilicon layer is formed over the buffer layer. Second impurities are implanted into the polysilicon layer, wherein the buffer layer prevents the oxide layer form being damaged by the second impurities. The polysilicon layer is etched to remove the polysilicon layer, wherein the buffer layer prevents the oxide layer and the substrate from being etched. The portion of buffer layer and the damaged oxide layer over the substrate are removed. The gate oxide layer is formed over the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.