Method for manufacturing a multilevel interconnection structure
US6033990A · kind A · utility
28Cited by
4References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 4, 1998 |
| Grant date | Mar 7, 2000 |
| Priority date | — |
| Expiry date | Mar 4, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76814
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating a semiconductor device on a silicon substrate comprises the step of high-frequency plasma-treatment for through-hole before filling the through-hole with a metallic layer for connection. The plasma contains argon, oxygen and hydrogen atoms wherein the ratio of oxygen atoms to the total of the oxygen and hydrogen atoms in number is between 1/3 and 1/100. The silicon substrate is applied with a high-frequency bias voltage during the plasma treatment for acceleration of argon ion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.