Method of forming variable thickness gate dielectrics

US6033998A · kind A · utility

Assignee

• LSI Logic Corporation · US

Inventors

• Sheldon Aronowitz · San Jose, US
• David Chan · San Jose, US
• James Kimball · San Jose, US
• David Lee · Sunnyvale, US
• John Haywood · Santa Clara, US
• Valeriy Sukharev · Cupertino, US

Key dates

• Filing date: Mar 9, 1998
• Grant date: Mar 7, 2000
• Expiry date: Mar 9, 2018

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/0144

Abstract

Provided is a method of fabricating gate dielectric layers having variable thicknesses and compositions over different regions of a semiconductor wafer. In a preferred embodiment of the present invention, a gate oxide layer is first grown over the various regions. Regions that are to have a relatively thicker, unhardened gate dielectric are masked and the wafer is exposed to a remote low energy nitrogen plasma. After the nitridization process is completed, the mask is removed and the wafer is exposed to further oxidation. The regions where oxynitrides have been formed act as a barrier to the oxidation process. Consequently, different oxide thicknesses can be grown on the same wafer, thinner and hardened where nitridization has been performed, and thicker and not hardened in those regions that were masked during the nitridization. Variable thickness gate dielectrics in accordance with the present invention may be particularly advantageous in semiconductor integrated circuits involving both digital and analog devices.