Electrostatic discharge protection for silicon-on-insulator
US6034399A · kind A · utility
15Cited by
14References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 6, 1997 |
| Grant date | Mar 7, 2000 |
| Priority date | — |
| Expiry date | Mar 6, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An ESD protection arrangement for a silicon-on-insulator device has an N-well type implant in the silicon substrate of the device, a p.sup.+ implant forming a juncture with the N-well type implant, and an n.sup.+ implant defining a juncture with the N-well type implant, in order to protect against negative transients and positive transients. At the p-channel threshold adjust, both the p-channel of the device and the N-well are implanted. Implanting the N-well to a depth of about 0.15 to about 0.30 .mu.m provides suitable characteristics for both the N-well and the p-channel.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.