Bus structure for modularized chip with FPGA modules
US6034542A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 14, 1997 |
| Grant date | Mar 7, 2000 |
| Priority date | — |
| Expiry date | Oct 14, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/177
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An on-chip bus structure for use in a modularized integrated circuit chip including an FPGA module(s). The bus is intended for memory mapped data transfers between circuit modules, for instance master, slave, master/slave, bus controller, and bus monitor type modules. Each circuit module is an on-chip function block including a bus interface and communicates by a predefined set of bus signals; at least one module is an FPGA (field programmable gate array). Each module acts as a bus master when it initiates data read or write operations, or may be addressed during a bus read/write operation and thereby acts as a bus slave. This bus and module structure allows implementation of a system on a single chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.