Programmable logic array structure having reduced parasitic loading
US6034543A · kind A · utility
1Cited by
3References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 12, 1997 |
| Grant date | Mar 7, 2000 |
| Priority date | — |
| Expiry date | Nov 12, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17708
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The present invention provides a PLA structure having logic interposed between an AND plane and an OR plane, wherein the interposed logic provides an additional set of minterms to the OR plane such that any PLA output function can be implemented with substantially fewer input signals. In this way, parasitic loading for implementation of any particular logic function is reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.