Multi-state flash memory defect management
US6034891A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 1, 1997 |
| Grant date | Mar 7, 2000 |
| Priority date | — |
| Expiry date | Dec 1, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system is described which stores data intended for defective memory cells in a row of a memory array in an overhead location of the memory row. The data is stored in the overhead packet during a write operation, and is read from the overhead packet during a read operation. A defect location table for the row of the memory array is provided to identify when a defective memory cell is address;ed for either a read or write access operation. During a write operation, the correct data is stripped from incoming data for storing into the overhead packet. During a read operation, the correct data is inserted into an output data stream from the overhead packet. Data written to defective cells can be either a custom setting, a default setting, or the original data. Shift registers are described for holding good data during either a read or write operation. The number of shift registers used is determined by the number of states stored in a memory cell. The shift registers use a marker for alignment ofdata bits in a data stream.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.