Floating point power conservation
US6035315A · kind A · utility
8Cited by
5References
4Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Oct 17, 1997 |
| Grant date | Mar 7, 2000 |
| Priority date | — |
| Expiry date | Oct 17, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/32
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus comprising floating point circuitry and first logic coupled to at least one flag in a processor control register (e.g. one of the control registers in the Intel Architecture brand processor or a processor compatible therewith) and the floating point circuitry and for coupling to a clock which drives the floating point circuitry. The first logic allows the clock to clock the floating point circuitry when the at least one flag has a first state. The first logic further prevents the clock from clocking the floating point circuitry when the at least one flag has a second state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.