Independent use of bits on an on-chip bus
US6035364A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 11, 1997 |
| Grant date | Mar 7, 2000 |
| Priority date | — |
| Expiry date | Dec 11, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4027
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A computer chip including multiple on-chip modules connected by an on-chip bus which provides increased performance over current computer chip architectures. The on-chip system bus is a bit sliced bus. Various transmitters/and or receivers are coupled the bit sliced bus. The transmitters and/or receivers include bus interface logic and/or bit transfer logic and/or bit receive logic operatively coupled to the on-chip bit sliced bus which operates to allow different data streams to use different bit lines substantially simultaneously. Thus the bit sliced bus allows different devices to share the bus simultaneously. The bus interface logic and/or the bit transfer logic thus may assign one data stream to a subset of the total bit lines on the bit sliced bus, and fill the unused bit lines with another data stream.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.