Method for fabricating a dual-gate dielectric module for memory embedded logic using salicide technology and polycide technology

US6037222A · kind A · utility

Assignee

• TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD. · TW

Inventors

• Kuo-Ching Huang
• Tse-Liang Ying · Baoshan, TW
• Chen-Jong Wang · Baoshan, TW
• Jenn Ming Huang · Baoshan, TW

Key dates

• Filing date: May 22, 1998
• Grant date: Mar 14, 2000
• Expiry date: May 22, 2018

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B12/05

Abstract

A method of manufacturing a memory device having embedded logic. The memory and logic FETS have two different two gate oxide 20 34 thicknesses. The method integrates (1) a salicide contact process 72 74 (logic devices) and dual gate (N+/P+) logic gate 24A 24B technology with (2) memory device Polycide with Self aligned Contact 80 Technology. The method comprises: PA1 (a) forming a first gate oxide layer 20, a first polysilicon layer 24, and a first gate cap layer 28 over said logic area 12; PA1 (b) forming memory gate structures 34 36 38 40 42A in memory area 14, PA1 (c) forming memory LDD regions 50 adjacent to said memory gate structures 24 26 28 40 in said memory area 14; PA1 (d) patterning said first gate oxide layer 20, said first polysilicon layer 24 and said first gate cap layer 28 over said logic area forming logic gate structures 20 24A & 20 24B; PA1 (e) forming spacers 66; PA1 (f) forming logic Source/drain regions 62; PA1 (g) using a salicide process to form self-aligned silicide logic S/D contacts 72 to said Source/drain regions 62, and to form self-aligned silicide logic gate contacts 74 to said logic gate structures 20 24B & 20 24A; and PA1 (h) forming self aligned po…