Method for forming a MOS structure having sidewall source/drain and embedded gate
US6037231A · kind A · utility
3Cited by
2References
18Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Nov 21, 1997 |
| Grant date | Mar 14, 2000 |
| Priority date | — |
| Expiry date | Nov 21, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/027
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A MOS device is provided with a reduced source and drain area. This is accomplished by first providing a MOS device with a buried gate region. The buried gate region is located on top of a channel region, which runs horizontally along the bottom of the gate trench. The source and drain regions are aligned vertically an parallel to the outside sidewalls of the buried gate region. Sidewall protectors are provided between the gate and lateral source and drain regions on the inside sidewalls of the gate trench. Additionally, a process for manufacturing the above described device is also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.