High-speed semiconductor device having a dual-layer gate structure and a fabrication process thereof
US6037245A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 28, 1999 |
| Grant date | Mar 14, 2000 |
| Priority date | — |
| Expiry date | Jun 28, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/20
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A fabricating process of a semiconductor device includes the steps of forming a first photoresist layer on a surface of a substrate so as to cover a gate electrode on the substrate, forming a second photoresist layer on the fist photoresist layer with an increased sensitivity, forming a third photoresist layer on the second photoresist layer with a reduced sensitivity, forming an opening in a photoresist structure thus formed of the first through third photoresist layers such that the opening exposes the gate electrode and such that the opening has a diameter that increases gradually from the first photoresist layer to the second photoresist layer. Further, a low-resistance metal layer is deposited on the photoresist structure including the opening, such that the metal layer forms a low-resistance electrode on the gate electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.