Method for making integrated circuit having polymer interlayer dielectric
US6037255A · kind A · utility
34Cited by
2References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 12, 1999 |
| Grant date | Mar 14, 2000 |
| Priority date | — |
| Expiry date | May 12, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/02282
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An improved method for making an integrated circuit that includes forming a conductive layer on a substrate, then forming a dielectric layer comprising a polymer on the conductive layer. After forming the dielectric layer, a layer of photoresist is patterned to define a region to be etched. An etched region is then formed through the dielectric layer while simultaneously removing the layer of photoresist.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.