High resolution multi-bit-per-cell memory
US6038166A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Apr 1, 1998 |
| Grant date | Mar 14, 2000 |
| Priority date | — |
| Expiry date | Apr 1, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5644
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A non-volatile, multi-bit-per-cell memory has a read circuit that includes a counter, a row line driver, and a sense circuit. During a read, the driver changes a read signal applied to the control gate of a selected memory cell being read. The counter simultaneously counts cycles of a clock signal. When the sense circuit sense a change in conductivity of the selected memory cell, the count in the counter indicates a multi-bit digital value corresponding to the threshold voltage of the selected memory cell and can be used to generate an output data signal. In one embodiment, the driver includes a digital-to-analog converter that generates the read signal. The converter is coupled to the counter so that a count from the counter controls the voltage of a read signal from the converter. The sense circuit can stop or disable the counter upon sensing a change in conductivity in a selected memory. The count is then output as a multi-bit digital value read from the selected memory cell. In another embodiment, multiple latches are coupled to the counter, and each latch corresponds to one of multiple memory cells that a read operation reads in parallel. As the counter counts, the sense circu…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.