Method and apparatus for a serial access memory
US6038185A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 12, 1998 |
| Grant date | Mar 14, 2000 |
| Priority date | — |
| Expiry date | May 12, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4096
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A serial memory device includes a Y decoder and sensing circuitry which provide a predictive mode of operation, wherein data sensing of a target memory location begins before its address is fully known by sensing the data lines of a number of possible memory locations including the target location. The method and apparatus includes sensing first data bits of possible memory locations when some but not all of the address bits are clocked in. As additional address bits are clocked in, additional data bits are sensed. By the time the target address has been fully received, sensing of its first data bits will have completed so that serial outputting of the target memory can begin on the next clock. This sense-ahead feature permits an increase in the internal clock frequency without affecting external timing constraints imposed by the various serial memory device interfaces.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.