2F-square memory cell for gigabit memory applications
US6040210A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 26, 1998 |
| Grant date | Mar 21, 2000 |
| Priority date | — |
| Expiry date | Jan 26, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B69/00
Abstract
A densely packed array of vertical semiconductor devices having pillars and methods of making thereof are disclosed. The array has columns of bitlines and rows of wordlines. The gates of the transistors act as the wordlines, while the source or drain regions acts as the bitlines. The array also has vertical pillars, each having a channel formed between source and drain regions. Two transistors are formed per pillar. This is achieved by forming two gates per pillar formed on opposite pillar sidewalls which are along the bitline direction. This forms two wordlines or gates per pillar arranged in the wordline direction. The source regions are self-aligned and located below the pillars. The source regions of adjacent bit lines are isolated from each other without increasing the cell size.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.