Stuart M. Burns
17Patents
15h-index
21Co-inventors
67Inventor score
Filing activity: Aug 6, 1996 → Dec 20, 1999
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6077745A | Self-aligned diffused source vertical transistors with stack capacitors in a 4F-square memory cell array | Electricity | 163 | Expired |
| US5874760A | 4F-square memory cell having vertical floating-gate transistors with self-aligned shallow trench isolation | Electricity | 137 | Expired |
| US5990509A | 2F-square memory cell for gigabit memory applications | Electricity | 100 | Expired |
| US6034389A | Self-aligned diffused source vertical transistors with deep trench capacitors in a 4F-square memory cell array | Emerging Cross-Sectional Technologies | 92 | Expired |
| US6033957A | 4F-square memory cell having vertical floating-gate transistors with self-aligned shallow trench isolation | Electricity | 61 | Expired |
| US6040210A | 2F-square memory cell for gigabit memory applications | Electricity | 60 | Expired |
| US6013548A | Self-aligned diffused source vertical transistors with deep trench capacitors in a 4F-square memory cell array | Emerging Cross-Sectional Technologies | 56 | Expired |
| US5895273A | Silicon sidewall etching | Electricity | 37 | Expired |
| US6040214A | Method for making field effect transistors having sub-lithographic gates with vertical side walls | Electricity | 33 | Expired |
| US5976986A | Low pressure and low power C1.sub.2 /HC1 process for sub-micron metal etching | Chemistry; Metallurgy | 25 | Expired |
| US6143635A | Field effect transistors with improved implants and method for making such transistors | Electricity | 24 | Expired |
| US6258679A | Sacrificial silicon sidewall for damascene gate formation | Electricity | 24 | Expired |
| US6268226A | Reactive ion etch loading measurement technique | Electricity | 23 | Expired |
| US5846884A | Methods for metal etching with reduced sidewall build up during integrated circuit manufacturing | Electricity | 18 | Expired |
| US6461529B1 | Anisotropic nitride etch process with high selectivity to oxide and photoresist layers in a damascene etch scheme | Electricity | 15 | Expired |
| US5759920A | Process for making doped polysilicon layers on sidewalls | Electricity | 13 | Expired |
| US6593617B1 | Field effect transistors with vertical gate side walls and method for making such transistors | Electricity | 1 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.