Method (and device) for producing tunnel silicon oxynitride layer
US6040216A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Feb 5, 1998 |
| Grant date | Mar 21, 2000 |
| Priority date | — |
| Expiry date | Feb 5, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/035
Abstract
A novel method of fabricating a flash memory cell. The present method includes a step of providing a semiconductor substrate (101) having a first active region (111), a second active region (109), and an isolation region (103). The isolation region is defined between the first active region and second active region. The process undergoes a step of masking (105) a portion of the isolation region and the second active region, and introducing (107) a nitrogen bearing impurity by implantation into a surface of the active region. The method also includes removing the portion being masked, e.g., stripping. A step of forming a silicon oxynitride layer (117) from the nitrogen bearing impurity on the surface of the first active region and forming silicon dioxide (115) on the second active region is included.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.