Method of fabricating polysilicon based resistors in Si-Ge heterojunction devices
US6040225A · kind A · utility
12Cited by
16References
7Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 29, 1997 |
| Grant date | Mar 21, 2000 |
| Priority date | — |
| Expiry date | Aug 29, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/615
Abstract
A method that enables the fabrication of ballast resistors in polysilicon which can be fabricated in a manner so as to not relax the strained layers in the lattice of the silicon germanium transistor wherein the high temperature steps, associated with activating dopants to fabricate resistors with desired resistance values, are performed prior to the deposited epitaxial layers of silicon germanium.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.