Fabrication of a SiC semiconductor device comprising a pn junction with a voltage absorbing edge
US6040237A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 23, 1997 |
| Grant date | Mar 21, 2000 |
| Priority date | — |
| Expiry date | Oct 23, 2017 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/931
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor component and a method for processing said component, which comprises a pn junction, where both the p-conducting (3) and the n-conducting layers (2) of the pn junction constitute doped silicon carbide layers and where the edge of the higher doped conducting layer of the pn junction exhibits a charge profile with a stepwise or uniformly decreasing total charge or effective surface charge density from the initial value at the main pn junction to a zero or almost zero total charge or charge density at the outermost edge of the junction following a radial direction from the central part of the junction towards the outermost edge.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.