Structure of a non-destructive readout dynamic random access memory
US6040595A · kind A · utility
3Cited by
7References
15Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 15, 1998 |
| Grant date | Mar 21, 2000 |
| Priority date | — |
| Expiry date | May 15, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/682
Abstract
A structure of dynamic random access memory includes a field effect transistor (FET), a capacitor, a world line and a bit line. The gate of the FET is electrically coupled to the word line in which a voltage source is supplied through the world line to the gate. The drain region of the FET is electrically coupled to a lower electrode of the capacitor. The capacitor has an upper electrode being electrically coupled to the gate of the FET either. The source region of the FET is electrically coupled to the bit line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.