Apparatus for read/write-access to registers having register file architecture in a central processing unit
US6041387A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 12, 1997 |
| Grant date | Mar 21, 2000 |
| Priority date | — |
| Expiry date | Sep 12, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3885
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processing unit has a set of data registers and a set of address registers. Each register has a width of n bits. Furthermore, there are provided address load and store buffers associated with the address registers, data load and store buffers associated with the data registers and a bus having a plurality of bus lines being connected to the store buffers. A data memory unit is connected to the bus. The data registers are arranged in such a way that at least n data registers are connected in parallel to respective bus lines, n being greater than 1, and the address registers are arranged in such a way, that at least m address registers are coupled in parallel to respective bus lines, m being greater than 1. Thus, at least four registers can be accessed in parallel.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.