Roger D. Arnold
16Patents
10h-index
16Co-inventors
69Inventor score
Filing activity: Mar 5, 1985 → Apr 10, 2006
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6128641A | Data processing unit with hardware assisted context switching capability | Physics | 49 | Expired |
| US4583725A | Patient support frame for posterior lumbar laminectomy | Human Necessities | 45 | Expired |
| US6292845A | Processing unit having independent execution units for parallel execution of instructions of different category with instructions having specific bits indicating instruction size and category respectively | Physics | 18 | Expired |
| US6434689B1 | Data processing unit with interface for sharing registers by a processor and a coprocessor | Physics | 18 | Expired |
| US6175913A | Data processing unit with debug capabilities using a memory protection unit | Physics | 17 | Expired |
| US7263599B2 | Thread ID in a multithreaded processor | Physics | 17 | Expired |
| US7047396B1 | Fixed length memory to memory arithmetic and architecture for a communications embedded processor system | Physics | 16 | Expired |
| US6378065B1 | Apparatus with context switching capability | Physics | 13 | Expired |
| US7062606B2 | Multi-threaded embedded processor using deterministic instruction memory to guarantee execution of pre-selected threads during blocking events | Emerging Cross-Sectional Technologies | 11 | Expired |
| US7546442B1 | Fixed length memory to memory arithmetic and architecture for direct memory access using fixed length instructions | Physics | 10 | Expired |
| US6041387A | Apparatus for read/write-access to registers having register file architecture in a central processing unit | Physics | 9 | Expired |
| US6859873B2 | Variable length instruction pipeline | Physics | 9 | Expired |
| US7159103B2 | Zero-overhead loop operation in microprocessor having instruction buffer | Physics | 8 | Expired |
| US7360203B2 | Program tracing in a multithreaded processor | Physics | 4 | Expired |
| US7260707B2 | Variable length instruction pipeline | Physics | 4 | Expired |
| US7774585B2 | Interrupt and trap handling in an embedded multi-thread processor to avoid priority inversion and maintain real-time operation | Physics | 1 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.