Read-only memory cell configuration with trench MOS transistor and widened drain region

US6043543A · kind A · utility

Assignee

• Siemens Aktiengesellschaft · DE

Inventor

• Helmut Klose · Munich, DE

Key dates

• Filing date: May 28, 1998
• Grant date: Mar 28, 2000
• Expiry date: May 28, 2018

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B20/00

Abstract

A read-only memory cell configuration and a method for its production include a substrate formed of semiconductor material having memory cells disposed in a cell field in a region of a main area. Each memory cell has at least one MOS transistor with a source region, a drain region, a channel region, a gate dielectric and a gate electrode. The drain region is connected to a bit line and the gate electrode is connected to a word line. The MOS transistor is formed by a trench starting at the main area and reaching as far as the source region. Side walls of the trench are disposed at an angle of approximately 45.degree. to approximately 80.degree. relative to the main area and are doped with a doping material of a predetermined conductivity for defining the programming of the MOS transistor.