Power factor correction method and apparatus
US6043633A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | Jun 5, 1998 |
| Grant date | Mar 28, 2000 |
| Priority date | — |
| Expiry date | Jun 5, 2018 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P80/10
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for controlling a boost converter, which offers improved power factor correction by compensating for the distorting effects of parasitic capacitance and parasitic oscillations. By precise adjustments to the closing time of the boost switch, the effects of parasitic capacitance can be reduced or eliminated. A zero current detector capable of detecting both forward and reverse zero current points facilitates the compensation. The method and circuit of the present invention are well-suited to integration with an inexpensive digital controller such as a microprocessor, and a method of dithering to enhance the time resolution of clocked digital circuits is presented.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.